`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:42:44 07/02/2015
// Design Name:   Etapa3
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Etapa3Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Etapa3
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Etapa3Test;

	// Inputs
	reg RegDst;
	reg RegWriteO;
	reg ALUSrc;
	reg PCSrc;
	reg MemRead;
	reg [3:0] MemWrite;
	reg MemToReg;
	reg [1:0] ALUOp;
	reg jmp;
	reg [2:0] LoadOp;
	reg [1:0] StoreOp;
	reg [2:0] InmCtrl;
	reg [31:0] E2Adder;
	reg [31:0] ReadData1;
	reg [31:0] ReadData2;
	reg [31:0] ExtSig;
	reg [4:0] RT;
	reg [4:0] RD;

	// Outputs
	wire [31:0] salidaALU;
	wire zeroFlag;
	wire [31:0] salidaAdder;
	wire [4:0] salidaMux;
	wire [31:0] Data2;
	wire RegWrite;
	wire PCSrc1;
	wire MemRead1;
	wire [3:0] MemWrite1;
	wire MemToReg1;
	wire [2:0] LoadOp1;
	//wire [1:0] StoreOp1;
	wire jmp1;

	// Instantiate the Unit Under Test (UUT)
	Etapa3 uut (
		.RegDst(RegDst), 
		.RegWriteO(RegWriteO), 
		.ALUSrc(ALUSrc), 
		.PCSrc(PCSrc), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.MemToReg(MemToReg), 
		.ALUOp(ALUOp), 
		.jmp(jmp), 
		.LoadOp(LoadOp), 
		.StoreOp(StoreOp), 
		.InmCtrl(InmCtrl), 
		.E2Adder(E2Adder), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2), 
		.ExtSig(ExtSig), 
		.RT(RT), 
		.RD(RD), 
		.salidaALU(salidaALU), 
		.zeroFlag(zeroFlag), 
		.salidaAdder(salidaAdder), 
		.salidaMux(salidaMux), 
		.Data2(Data2), 
		.RegWrite(RegWrite), 
		.PCSrc1(PCSrc1), 
		.MemRead1(MemRead1), 
		.MemWrite1(MemWrite1), 
		.MemToReg1(MemToReg1), 
		.LoadOp1(LoadOp1), 
		.jmp1(jmp1)
	);

	initial begin
		// Initialize Inputs
		RegDst = 0;
		RegWriteO = 0;
		ALUSrc = 0;
		PCSrc = 0;
		MemRead = 0;
		MemWrite = 0;
		MemToReg = 0;
		ALUOp = 0;
		jmp = 0;
		LoadOp = 0;
		StoreOp = 0;
		InmCtrl = 0;
		E2Adder = 0;
		ReadData1 = 0;
		ReadData2 = 0;
		ExtSig = 0;
		RT = 0;
		RD = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add 
		RegDst = 1;
		RegWriteO = 1;
		ALUSrc = 0;
		PCSrc = 0;
		MemRead = 0;
		MemWrite = 0;
		MemToReg = 0;
		ALUOp = 2'b 10;
		jmp = 0;
		LoadOp = 3'b xxx;
		StoreOp = 2'b xx;
		InmCtrl = 0;
		E2Adder = 0;
		ReadData1 = 32'h ffff0000;
		ReadData2 = 32'h 0000ffff;
		ExtSig = 32'h 00001020;
		RT = 5'b 1;
		RD = 5'b 10;
		//AddI
		#200;
		RegDst = 0;
		RegWriteO = 1;
		ALUSrc = 1;
		PCSrc = 0;
		MemRead = 0;
		MemWrite = 0;
		MemToReg = 0;
		ALUOp = 2'b 11;
		jmp = 0;
		LoadOp = 3'b xxx;
		StoreOp = 2'b 01;
		InmCtrl = 0;
		E2Adder = 32'h 0000000c;
		ReadData1 = 32'h ffff0000;
		ReadData2 = 32'h xxxxxxxx;
		ExtSig = 32'h 00000016;
		RT = 5'h 0d;
		RD = 0;
	end


      
endmodule

